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VHDL Setup and Simulation


VHDPlus IDE0.9+Instructions
Packages-GHDL or ModelSim

Video Tutorial

Written tutorial


  1. (Optional) Open Extras > Package manager and install the VHDL Language Support
  2. (Optional) Open Extras > Settings > Editor and select what support you want to use

You can click on File > Import Quartus Project to import an existing VHDL project

Create a VHDL project

  1. Create a new project and select VHDL Project with Simulation. An example for a blinking LED will be created.
blink: process(clk)
if rising_edge(clk) then
if counter < 1000000 then
counter <= counter + 1;
counter <= 0;
end if;
end if;
end process blink;
  1. A testbench file will be created where the clock signal is simulated. An instance of the blink code is created and simulated.
clk_proc: process
while finished /= '1' loop
CLK <= '0';
wait for period_time/2;
CLK <= '1';
wait for period_time/2;
end loop;
end process clk_proc;

u1: Demo
port map

Here you can find more information on creating testbenches for you VHDL code

Start the simulation

  1. Do a right click on the testbench file and select Simulate with GHDL or Simulate with Modelsim
  2. Check for errors in the output window


  1. After GTK Wave is open, click on the component of which you want to see the signal
  2. Double click the signal to display in the wave window
  3. You can zoom out and see the simulated behavior

For Modelsim:

  1. After Modelsim is open, right click the signal to simulate and click on Add to Wave. Or you can just drag an drop the signals.
  2. Select the Run Length and run the simulation with the buttons on top
  3. You can zoom out and see the simulated behavior

Done ✔ Need help?

If everything worked as planned, the LED of your FPGA should blink every second.
If anything went wrong, feel free to ask for help. For the fastest response, join us on Discord.